The present invention is directed to a power supply scheme where the differential amplifier supply and the reference supply will track each other, thereby reducing the receiver timing mismatches in source synchronous and common clock designs.
Computers and other types of electronic equipment often utilize a series of chips to perform different functions for the overall device. In each chip there is a core which performs the main function of the chip and is surrounded by an input/output (I/O) ring with each I/O device in the ring forming a communication link with another chip. Each of these I/O devices may be connected to the other chips by way of an interface.
The core logic devices can operate at a very high frequency, so it is important that the interfaces and I/O devices should operate as fast as possible to keep up with the core speed. One problem with such high speed signaling is the receiver timing errors, which are the errors that occur in source synchronous and common clock designs where there is a delay mismatch between the data signal and the strobe or clock signals. The strobe signals act as a clock to latch the data signals at a specific time. These errors may be caused by a number of different problems. One such problem is the slew rate mismatch between data and the strobe signals. Another is variation in the chips due to manufacturing process variations and a third is variation in the power supplies. Different chips have their own voltage supplies and also different parts of the overall device may rely on different power sources.
In particular, buffers are often used in the interface devices between chips. These buffers include differential amplifiers and other logic devices which process the input signals. The differential amplifiers require a reference voltage to which the input signal level is compared to determine its bit value. Variations in the voltage sources which supply the differential amplifier supply and reference voltage supply can result in unacceptable receiver timing errors.